In self-synchronous systems, there may be a critical timing delay, referred to as clock-to-data loop delay (or simply loop delay), for example from the time a clock signal is launched from a host to a device to the time that data requested by the host may be made available by the device. When the host has requested data from the device, the host may launch the clock signal and then expect the requested data within a certain timing window. The clock signal may travel on a clock line to the device, the device may then process the requested data based on the clock signal, and finally the device may make the requested data available to the host by sending the requested data on a data line back to the host. If the data is made available within the timing window, then the read operation may be performed successfully. However, if the data is not made available within the timing window, then the host may determine a timeout event and/or that the device is unable to send the requested data back to the host.
The timing window may be measured in terms of unit intervals (UI). For lower operating frequencies (e.g., around 100 Megahertz (MHz), the timing window may be one unit interval (1UI) in duration. For higher operation frequencies (e.g., 208 MHz), the timing window may be two unit intervals (2UI) in duration. For 2UI timing window configurations, the host may perform a tuning sequence within the 2UI timing window to determine the availability of the requested data, and then align its lock state using delay locked loop (DLL) circuitry.
The host and device may communicate data, clock, and command signals with each other according to an operating voltage. In multi-voltage environments, the operating voltage may be at a first, higher level or at second, lower level. Example operating voltages may be 3.3 Volts (V) and 1.8 V. The transistors configured in a critical path of the device that are used to receive the clock signal from the host and generate the data signal for sending to the host may have a certain gate thickness that optimizes area and reliability. However, the delay caused by the transistors when processing the signals may differ for the different operating voltage levels due to large loading. In particular, when the transistors are operating at the lower voltage level, the delay may be significantly higher, such as around four times greater for example, compared to when the transistors are operating at the higher voltage level. As a result, while the transistors may provide an adequately small amount of delay when operating at the higher voltage level (i.e. a delay that causes data to be available within the specified timing window), they may provide too large of a delay when operating at the lower voltage level (i.e., a delay that causes data to be available only after the timing window has lapsed). So that requested data may be available within the specified timing window, devices configured with reduced loop delay may be desirable.